Bipolar pulsed-voltage gate driver

ABSTRACT

A gate driver circuit comprises a gate-driver assembly, a transformer, first and second circuit voltage outputs, first and second switching devices, and a controller. The gate-driver assembly comprises a first and second voltage inputs and a first and second voltage outputs coupled to a primary winding of the transformer. The first and second switching devices are coupled to the secondary winding and respectively coupled to the first and second circuit voltage outputs. The controller is configured to cause the first circuit voltage output to supply a positive output voltage by supplying a higher first input voltage to the first voltage input than to the second voltage input and is also configured to cause the first circuit voltage output to supply a negative output voltage by supplying a higher second input voltage to the second voltage input than to the first voltage input.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit and priority of U.S. applicationSer. No. 17/192,177, filed Mar. 4, 2021. The entire disclosure of theabove application is incorporated herein by reference.

TECHNICAL FIELD

Aspects of the disclosure are related to power supplies and, inparticular, to power supply gate drivers.

BACKGROUND

A power supply typically converts an incoming voltage into a different,output voltage. For example, an alternating current (AC) input voltagemay be converted to a direct current (DC) voltage for use by electronicequipment. In another example, a first DC input voltage may be convertedto a different DC voltage for use by the electronic equipment.

Power supply topologies can include driving a high-side or floatingsemiconductor switch. These topologies include, for example, a buckconverter, an LLC converter, a half-bridge converter, a full-bridgeconverter, a totem-pole boost converter, etcetera. Known solutions todriving the high-side semiconductor switch include using a bootstrapgate driver circuit, an isolated gate driver circuit, or differentvariations of transformer gate driver circuits. Such solutions can havea reduced duty cycle range of the semiconductor switch and can affectimplementation costs.

OVERVIEW

In accordance with one aspect, a gate driver circuit comprises agate-driver assembly, a transformer, first and second circuit voltageoutputs, first and second switching devices, and a controller. Thegate-driver assembly comprises a first voltage input and a first voltageoutput configured to provide a first output voltage based on a firstinput voltage supplied to the first voltage input. The gate-driverassembly also comprises a second voltage input and a second voltageoutput configured to provide a second output voltage based on a secondinput voltage supplied to the second voltage input. The transformercomprises a primary winding coupled to the first voltage output and tothe second voltage output and comprises a secondary winding. The firstswitching device is coupled to the secondary winding and coupled to thefirst circuit voltage output, and the second switching device is coupledto the secondary winding and coupled to the second circuit voltageoutput. The controller is configured to cause the first circuit voltageoutput to supply a positive output voltage with respect to an outputvoltage supplied by the second circuit voltage output by supplying ahigher first input voltage to the first voltage input than a secondinput voltage supplied to the second voltage input. The controller isalso configured to cause the first circuit voltage output to supply anegative output voltage with respect to the output voltage supplied bythe second circuit voltage output by supplying a higher second inputvoltage to the second voltage input than the first input voltagesupplied to the first voltage input.

In accordance with another aspect, a power supply circuit comprises ahigh-side switching device and a high-side gate driver having a voltageoutput. The high-side gate driver comprises a gate-driver assemblycomprising a pair of voltage inputs and a pair of voltage outputs, atransformer having a primary winding and a secondary winding, and a pairof switching devices coupled to the secondary winding and to the voltageoutput. A controller is configured to control the high-side switchingdevice into an on state by causing the gate-driver assembly to supply acurrent from a first output of the pair of voltage outputs to a secondoutput of the pair of voltage outputs through the primary winding. Thecontroller is also configured to control the high-side switching deviceinto an off state by causing the gate-driver assembly to supply thecurrent from the second output to the first output through the primarywinding.

In accordance with another aspect, a method comprises applying a firstvoltage to a first input of a gate-driver assembly and applying a secondvoltage to a second input of the gate-driver assembly, the first voltagehigher than the second voltage. In response to the application of thefirst and second voltages, the method comprises causing a positivecurrent to flow through a primary winding of a transformer from a firstoutput of the gate-driver assembly to a second output of the gate-driverassembly. In response to the positive current flowing through theprimary winding, the method comprises causing a positive inductivecurrent to flow through a secondary winding of the transformer. Inresponse to the positive inductive current flowing through the secondarywinding, the method comprises causing a pair of switches coupled to thesecondary winding to provide a positive output voltage to a switchingdevice, the switching device configured to turn on in response to thepositive output voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings illustrate embodiments presently contemplated for carryingout embodiments of the present disclosure.

In the drawings:

FIG. 1 illustrates a schematic block diagram of a power electroniccircuit according to an embodiment of the present disclosure.

FIG. 2 illustrates a gate driver circuit according to an embodiment.

FIG. 3 illustrates a gate driver circuit according to anotherembodiment.

FIG. 4 illustrates waveforms of a control scheme according to anembodiment.

FIG. 5 illustrates current flow in the gate driver circuit of FIG. 2during a rising-edge delay according to an embodiment.

FIG. 6 illustrates current flow in the gate driver circuit of FIG. 2during a falling-edge delay according to an embodiment.

FIG. 7 illustrates waveforms of a control scheme according to anotherembodiment.

FIG. 8 illustrates waveforms of a control scheme according to anotherembodiment.

FIG. 9 illustrates a power electronic circuit according to anotherembodiment.

While the present disclosure is susceptible to various modifications andalternative forms, specific embodiments thereof have been shown by wayof example in the drawings and are herein described in detail. It shouldbe understood, however, that the description herein of specificembodiments is not intended to limit the present disclosure to theparticular forms disclosed, but on the contrary, the intention is tocover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the present disclosure. Note that correspondingreference numerals indicate corresponding parts throughout the severalviews of the drawings.

DETAILED DESCRIPTION

Examples of the present disclosure will now be described more fully withreference to the accompanying drawings. The following description ismerely exemplary in nature and is not intended to limit the presentdisclosure, application, or uses.

Example embodiments are provided so that this disclosure will bethorough, and will fully convey the scope to those who are skilled inthe art. Numerous specific details are set forth such as examples ofspecific components, devices, and methods, to provide a thoroughunderstanding of embodiments of the present disclosure. It will beapparent to those skilled in the art that specific details need not beemployed, that example embodiments may be embodied in many differentforms and that neither should be construed to limit the scope of thedisclosure. In some example embodiments, well-known processes,well-known device structures, and well-known technologies are notdescribed in detail.

Although the disclosure hereof is detailed and exact to enable thoseskilled in the art to practice the invention, the physical embodimentsherein disclosed merely exemplify the invention which may be embodied inother specific structures. While the preferred embodiment has beendescribed, the details may be changed without departing from theinvention, which is defined by the claims.

FIG. 1 illustrates schematic block diagram of a power electronic circuitbuilding block 100 according to an embodiment of the present disclosure.Driving semiconductor switches on and off is a fundamental aspect of anypower electronics circuit. A common building block of power electroniccircuits is the half-bridge configuration as shown in FIG. 1. Buildingblock 100 includes two power semiconductor switches: a high-side switch102 and a low-side switch 104. As illustrated in FIG. 1, the switches102, 104 are active switches and include transistors (e.g., metal oxidesemiconductor field-effect transistors (MOSFETs)). Embodiments of thedisclosure, however, contemplate the use of alternative activelycontrolled switches, passive switches, and the like for either or bothswitches. The switches 102, 104 are connected in series between a firstvoltage 106 (e.g., V_(bulk)) and a circuit ground 108. The switches 102,104 are turned on and off by their respective gate driver circuit 110,112 driven by a pulse width modulation (PWM) generator PWM generator 114configured to generate one or more PWM signals 116 to drive each gatedriver circuit 110, 112. Driving the low-side switch 104 is often astraightforward task using known techniques since the circuitry in thegate driver circuit 112 is referenced to ground 108. The low-side switch104 can, therefore, be driven by a low-cost low-side gate driver 112.Driving the high-side switch 102 is not as simple as the gate drivercircuit because driving this switch involves the gate driver circuit 110being referenced to a switch-node voltage 118 (e.g., V_(sw)).

Known techniques for driving the high-side switch 102 on and offinclude: 1) level shifting the PWM signal and using a bootstrap circuitto create a floating supply voltage that powers the high-side gatedriver, 2) using an isolated gate driver circuit that is powered by anisolated direct current (DC) supply, or 3) using different types oftransformer gate drive circuits. These known techniques have differenttrade-offs when it comes to circuit cost, circuit footprint, circuitpower dissipation, wide duty-cycle operation, and current sourcing andsinking capability. In addition, trade-offs exist regarding dv/dt anddi/dt noise immunity.

FIG. 2 illustrates a bipolar pulsed-voltage gate driver circuit 200 forthe high-side gate driver circuit 110 of FIG. 1 according to anembodiment that overcomes some of the aforementioned drawbacks. The gatedriver circuit 200 includes a dual gate-driver assembly 202 having apair of buffers 204, 206, each having a voltage input 208 coupled to asource voltage 210 and having a ground input 212 coupled to a signalground 214.

The dual gate-driver assembly 202 has a first voltage input 216configured to receive a first input voltage, and a first voltage output218 is configured to supply a first output voltage signal in response toreceiving the first input voltage. For example, a high input voltagesignal received on the first voltage input 216 results in a high outputvoltage signal transmitted by the first voltage output 218. In addition,a second voltage input 220 and a second voltage output 222 are alsoincluded for supplying a second output voltage signal on the secondvoltage output 222 in response to receiving a high input voltage signalon the second voltage input 220.

In the gate driver circuit 200, a resistor 224 and a primary winding 226of a transformer 228 are coupled in series between the first voltageoutput 218 and the second voltage output 222. The resistor 224 isconfigured to limit current flow between the outputs 218, 222 and thusin the primary side of the transformer 228, which in turn limits currentflow in the secondary side of the transformer 228. In this manner,resistor 224 limits current flowing out of the gate driver circuit 200and into a transistor gate (e.g., a gate of high-side switch 102 of FIG.1). A secondary side of the transformer 228 includes a secondary winding230 coupled to a first transistor 232 and a second transistor 234.Transistors 232, 234 include n-type transistors (e.g., n-type MOSFETs).As used herein, n-type transistors are those created by doping with anelectron donor element during manufacture. As illustrated, a high-sideterminal 236 of the secondary winding 230 is coupled to a sourceterminal 238 of the first transistor 232 and to a gate terminal 240 ofthe second transistor 234. A low-side terminal 242 of the secondarywinding 230 is coupled to a source terminal 244 of the second transistor234 and to a gate terminal 246 of the first transistor 232. The drainterminals 248, 250 of the transistors 232, 234 are coupled to respectiveoutput terminals 252, 254 of the gate driver circuit 200. Body diodes256, 258 formed between the drain terminals 248, 250 and the sourceterminals 238, 244 of the respective transistor 232, 234 are representedusing diode symbols.

FIG. 3 illustrates a bipolar pulsed-voltage gate driver circuit 300according to an embodiment. The gate driver circuit 300 of FIG. 3 issimilar to the gate driver circuit 200 of FIG. 2 with the dualgate-driver assembly 202 of FIG. 2 being implemented with a dualgate-driver integrated circuit (IC) 302 such as one commonly availablein the marketplace. While placed into the high-side switch drivingcircuit as described herein, the dual gate-driver IC 302 may be one thatis typically used to drive the low-side switch 104. The operation andcontrol of the gate driver circuit 300 is similar or identical to thegate driver circuit 200, and either circuit 200 or 300 may be controlledin the manner described herein.

FIG. 4 illustrates waveforms of a control scheme 400 according to anembodiment. Referring to FIGS. 2 and 4, operation of the gate drivercircuit 200 as a high-side switch driver includes two separate PWMsignals, v_(pwmA) and v_(pwmB), provided by one or more PWM generatorsor controllers (e.g., a microcontroller) such as PWM generator 114 ofFIG. 1. In one embodiment, the PWM signals are digital PWM (DPWM)signals 402, 404 that are separated by a rising-edge delay 406 and afalling-edge delay 408. Separation of the DPWM signals 402, 404 by therising-edge delay 406 creates a positive pulse 410 across the primarywinding 226 of the transformer 228 having a pulse width substantiallyequal to the width of the rising-edge delay 406. FIG. 5 illustratescurrent flow during application of the DPWM signal 402 prior to theapplication of the DPWM signal 404 during the rising-edge delay 406. Inresponse to the DPWM signal 402 (e.g., v_(pwmA)) applying a voltage(e.g., V_(dd)) to the first voltage input 216, current (illustrated inFIG. 4 as i_(drv)) flowing from first voltage output 218 to secondvoltage output 222 generates a primary voltage (e.g., V_(cc)) across theprimary winding 226 of the transformer 228. Since the DPWM signal 404 islow during this time, the second voltage output 222 operates as acurrent sink to allow the current flow through the primary winding 226.A current induced in the secondary winding 230 (e.g., inductive current)generates a secondary voltage (e.g., V_(cc)) based on a turns ratio ofthe primary winding 226 to the secondary winding 230 (e.g., 1:1 as usedherein). The positive secondary voltage turns the second transistor 234on, and the output terminals 252, 254 are charged to a positive voltage412 (e.g., V_(cc)-V_(sd)), where V_(sd) is the voltage dropped acrossthe body diode 256 of the first transistor 232. The positive voltage 412includes the output voltage supplied by the output terminal 252 beinghigher than the output voltage supplied by the output terminal 254. Theoutput terminals 252, 254 thus supply a positive voltage (e.g., V_(gsl))across the gate and source terminals of the high-side switch 102 of FIG.1, turning the high-side switch 102 on and allowing it to conduct thevoltage V_(bulk) to the load.

At the expiration of the rising-edge delay 406, the DPWM signal 404(e.g., v_(pwmB)) applies a voltage similar to the voltage supplied bythe DPWM signal 402 (e.g., V_(dd)), which reduces or eliminates thecurrent flow between the first voltage output 218 to second voltageoutput 222 such that the primary and secondary voltages return to aminimal value such as 0 V. That is, the DPWM signal 404 applies avoltage substantially similar to the voltage supplied by the DPWM signal402. As used herein, the voltages supplied by DPWM signals 402 and 404are substantially similar when no current flows from one voltage output218 to the other voltage output 222 or vice versa or when any currentflowing therebetween fails to cause either of the transistors 232, 234to turn on. With the loss of the secondary voltage value, the secondtransistor 234 is turned off. Since the first transistor 232 is off andsince reverse current flow from the output terminal 252 to the firsttransistor 232 is prevented by the body diode 256, the voltage acrossthe output terminals 252, 254 and thus the gate charge applied to thehigh-side switch 102 is halted and held, keeping the high-side switch102 in a conducting, on state. FIG. 4 illustrates the voltage pulsegenerated across the secondary winding 230 of the transformer 228 duringthe rising-edge delay 406 as positive pulse 410.

The high-side switch 102 is turned off during the falling-edge delay 408in which the current flow through the primary winding 226 of thetransformer 228 is reversed as compared with the current flow during therising-edge delay 406. To reverse the current (as illustrated in FIG.6), the DPWM signal 402 (e.g., v_(pwmA)) drops the voltage applied tothe first voltage input 216 at the beginning of the falling-edge delay408 while the DPWM signal 404 (e.g., v_(pwmB)) maintains the voltagepreviously applied. The loss of the applied voltage to the first voltageinput 216 allows the current from the output terminal 254 to be sunkinto the output terminal 252, creating a negative voltage (e.g.,—V_(cc))across the primary and secondary windings 226, 230 of the transformer228. The negative voltage turns the first transistor 232 on and chargesthe output terminals 252, 254 to a negative voltage 414(e.g.,—V_(cc)+V_(sd)), which supplies a negative voltage (e.g.,—V_(gsl))across the gate and source terminals of the high-side switch 102 of FIG.1, turning the high-side switch 102 off. The negative voltage 414includes the output voltage supplied by the output terminal 254 beinghigher than the output voltage supplied by the output terminal 252. Atthe expiration of the falling-edge delay 408, the DPWM signal 404 (e.g.,v_(pwmB)) drops the voltage previously applied, which reduces oreliminates the current flow between the first voltage output 218 tosecond voltage output 222 such that the primary and secondary voltagesreturn to a minimal value such as 0 V. With the loss of the secondaryvoltage value, the first transistor 232 is turned off. Since the secondtransistor 234 is off and since reverse current flow from the outputterminal 254 to the second transistor 234 is prevented by the body diode258, the voltage across the output terminals 252, 254 and thus the gatecharge applied to the high-side switch 102 is held, keeping thehigh-side switch 102 in a non-conducting, off state. FIG. 4 illustratesthe voltage pulse generated across the secondary winding 230 of thetransformer 228 during the falling-edge delay 408 as a negative pulse416.

The DPWM signals 402 described herein may be generated and provided bythe PWM generator 114 illustrated in FIG. 1. Alternatively, anothercontroller capable of providing the DPWM signals may be used. A variablepulse width may be implemented in order to achieve a duty-cycle controlof the gate-source voltage V_(gsl) 418 controlling the switch (e.g.,high-side switch 102 of FIG. 1) in the range from 0% to 100%. The dutycycle of the gate-source voltage may be calculated based on the ratio ofthe time DT 420 that the gate-source voltage 418 provides the positivevoltage 412 to the time T 422 between a rising edge of one positivevoltage 412 to the rising edge of the next positive voltage 412. Byvarying the time T 422, different frequencies of the gate-source voltagecan also be achieved.

The variable pulse width for controlling the duty cycle can beimplemented using variable edge-delay timing on the v_(pwmA) andv_(pwmB) PWM signals. As illustrated in FIG. 4, a turn-on pulse delay424 exists between generation of the positive pulse 410 and thecorresponding negative pulse 416, and a turn-off pulse delay 426 existsbetween the negative pulse 416 and the next positive pulse 410. Wheneach delay 424, 426 is greater than zero seconds, the duty cycle may beconsidered to be variable within a middle range. In the middle range,the length of time during which the positive and negative pulses 410,416 are on provides a sufficient delay to correspondingly turn thehigh-side switch 102 on and off. That is, the time length of thepositive pulse 410, for example, is at least as long as any circuitdelay inherent in receiving the rising edge of the DPWM signal 402(while the DPWM signal 404 is still low) and generating the resultingpositive voltage 412 at the output terminals 252, 254. The time lengthof the positive pulse 410 can include an additional time buffer toensure turn-on of the high-side switch 102. The time length of thenegative pulse 416 is similarly controlled. The time lengths of thepositive and negative pulses 410, 416 may be the same or different.

Holding time T 422 constant, the duty cycle of the gate-source voltage418 increases or decreases with a respective increase or decrease of thelength of the turn-on pulse delay 424 (and corresponding change to theturn-off pulse delay 426). The duty cycle of the gate-source voltage 418can also increase or decrease holding the turn-on pulse delay 424constant while respectively decreasing or increasing the turn-off pulsedelay 426. Other combinations of varying the turn-on pulse delay 424 andthe turn-off pulse delay 426 will result in corresponding changes to theduty cycle and/or the frequency of the gate-source voltage 418. As thelength of the turn-on pulse delay 424 decreases, the duty cycle of thegate-source voltage 418 decreases, and the frequency of the gate-sourcevoltage 418 stays the same. As the length of the turn-on pulse delay 424increases while the length of the time T 422 remains constant, the dutycycle of the gate-source voltage 418 increases, and the frequency of thegate-source voltage 418 stays the same.

FIG. 7 illustrates waveforms of the control scheme 400 of FIG. 4according to another embodiment. As illustrated, the positive andnegative pulses 410, 416 have been brought together through theelimination of the turn-on pulse delay 424. In this embodiment, the dutycycle may be considered to be variable within a low range. In the lowrange, the negative pulse 416 is held to a constant pulse width toensure that the gate of the high-side switch 102 is pulled to thenegative voltage 414 every switching cycle. The pulse width of thepositive pulse 410, however, may be less than the width of the positivepulse 410 in the middle range (e.g., FIG. 4) and may even be reduced allthe way to zero. In this low range, the width of the positive voltage412 is substantially equal to the width of the positive pulse 410.

FIG. 8 illustrates waveforms of the control scheme 400 of FIG. 4according to another embodiment. As illustrated, the positive andnegative pulses 410, 416 have been brought together through theelimination of the turn-off pulse delay 426. In this embodiment, theduty cycle may be considered to be variable within a high range. In thehigh range, the positive pulse 410 is held to a constant pulse width toensure that the gate of the high-side switch 102 is pulled to thepositive voltage 412 every switching cycle. The pulse width of thenegative pulse 416, however, may be less than the width of the negativepulse 416 in the middle range (e.g., FIG. 4) and may even be reduced allthe way to zero. In this high range, the width of the negative voltage414 is substantially equal to the width of the negative pulse 416.

FIG. 9 illustrates a power electronic circuit 900 according to anotherembodiment. The power electronic circuit 900 includes the gate drivercircuit 300 of FIG. 3 and the high-side switch 102 and PWM generator 114of FIG. 1. Unlike FIG. 1, FIG. 9 does not include the low-side switch104 but instead illustrates a switching device 902 implemented as adiode in place of the low-side switch 104. However, operation of the PWMgenerator 114 and the gate driver circuit 300 to turn the high-sideswitch 102 on and off may be controlled as described hereinabove.

Embodiments of the disclosure operate to drive a high-side switch usinga gate driver circuit that benefits from a galvanically isolated, lowprinted circuit board footprint. Embodiments described herein comprise asingle dual low-side gate driver, a small low-volt-seconds ratedtransformer, a good ability to source and sink current, and have agenerally low part cost. Further, a circuit based on the embodimentsdescribed herein allow the high-side switch to operate from a 0% dutycycle to a 100% duty cycle depending on the control of the PWM signalsused to drive the gate driver.

While the invention has been described in detail in connection with onlya limited number of embodiments, it should be readily understood thatthe invention is not limited to such disclosed embodiments. Rather, theinvention can be modified to incorporate any number of variations,alterations, substitutions or equivalent arrangements not heretoforedescribed, but which are commensurate with the spirit and scope of thepresent disclosure. Additionally, while various embodiments of thepresent disclosure have been described, it is to be understood thataspects of the present disclosure may include only some of the describedembodiments. Accordingly, the invention is not to be seen as limited bythe foregoing description but is only limited by the scope of theappended claims.

1. (canceled)
 2. A gate driver circuit comprising: a transformercomprising a secondary winding having a high-side terminal and alow-side terminal; a first voltage output; a first switching devicecomprising: a first terminal coupled with the high-side terminal; asecond terminal coupled with the first voltage output; and a thirdterminal; a second voltage output; a second switching device comprising:a first terminal coupled with the low-side terminal and the thirdterminal of the first switching device; a second terminal coupled withthe second voltage output; and a third terminal coupled with the firstterminal of the first switching device and with the high-side terminal;and wherein the third terminal of the first switching device is coupledwith the first terminal of the second switching device and with thelow-side terminal.
 3. The gate driver circuit of claim 2, wherein: thefirst switching device comprises a metal oxide semiconductorfield-effect transistor (MOSFET); the first terminal of the firstswitching device comprises a source; the second terminal of the firstswitching device comprises a drain; the third terminal of the firstswitching device comprises a gate; the second switching device comprisesa MOSFET; the first terminal of the second switching device comprises asource; the second terminal of the second switching device comprises adrain; and the third terminal of the second switching device comprises agate.
 4. The gate driver circuit of claim 2 further comprising a firstvoltage input and a second voltage input; wherein the first voltageoutput is configured to provide a first output voltage based on a firstinput voltage supplied to the first voltage input; and wherein thesecond voltage output configured to provide a second output voltagebased on a second input voltage supplied to the second voltage input. 5.The gate driver circuit of claim 4 further comprising a controllerconfigured to: cause the first voltage output to supply a positiveoutput voltage with respect to an output voltage supplied by the secondvoltage output by supplying a higher first input voltage to the firstvoltage input than the second input voltage supplied to the secondvoltage input; and cause the first voltage output to supply a negativeoutput voltage with respect to the output voltage supplied by the secondvoltage output by supplying a higher second input voltage to the secondvoltage input than the first input voltage supplied to the first voltageinput.
 6. The gate driver circuit of claim 5, wherein supplying thehigher first input voltage causes the second switching device to turnon.
 7. The gate driver circuit of claim 6, wherein the controller isfurther configured to cause the second switching device to turn off bysupplying the second input voltage at a voltage substantially matchingthe first input voltage while a portion of the first input voltage isbeing supplied to the first voltage input.
 8. The gate driver circuit ofclaim 7, wherein supplying the higher second input voltage causes thefirst switching device to turn on.
 9. The gate driver circuit of claim8, wherein the controller is further configured to cause the firstswitching device to turn off by supplying the first input voltage at avoltage substantially matching the second input voltage while a portionof the second input voltage is being supplied to the second voltageinput.
 10. The gate driver circuit of claim 5, wherein the controller isfurther configured to vary a time interval between the positive outputvoltage and the negative output voltage to control a pulse-widthmodulation (PWM) output of a load switching device coupled to the firstvoltage output and to the second voltage output.
 11. The gate drivercircuit of claim 2, wherein the transformer further comprises a primarywinding; and wherein the gate driver circuit further comprises a dualgate-driver assembly coupled between the primary winding and the firstand second voltage inputs.
 12. The gate driver circuit of claim 11,wherein the dual gate-driver assembly comprises a dual gate-driverintegrated circuit (IC).
 13. A method comprising: applying a voltagedifferential across first and second inputs of a gate-driver assembly tocause a positive current to flow through a primary winding of atransformer from a first output of the gate-driver assembly to a secondoutput of the gate-driver assembly; in response to the positive currentflowing through the primary winding: causing a positive inductivecurrent to flow through a secondary winding of the transformer; andcausing a pair of switches coupled to the secondary winding to provide apositive output voltage to a switching device, the switching deviceconfigured to turn on in response to the positive output voltage; andapplying a common voltage across the first and second inputs after afirst delay to reduce the positive current flow through the primarywinding.
 14. The method of claim 13 further comprising causing the pairof switches to halt providing the positive output voltage to theswitching device in response to reducing the positive current flowthrough the primary winding.
 15. The method of claim 13, whereinapplying the voltage differential across the first and second inputscomprises: applying a first voltage to the first input; and applying asecond voltage to the second input, the first voltage higher than thesecond voltage.
 16. The method of claim 15, wherein applying the firstvoltage to the second input comprises applying the first voltage to thesecond input while simultaneously applying the first voltage to thefirst input.
 17. The method of claim 16, wherein applying the secondvoltage to the second input after the first delay comprises applying thesecond voltage to the second input after the first delay to eliminatethe positive current flow.
 18. The method of claim 13 furthercomprising: applying a second voltage differential across the first andsecond inputs of the gate-driver assembly to cause a negative current toflow through the primary winding from the second output of thegate-driver assembly to the first output of the gate-driver assembly; inresponse to the negative current flowing through the primary winding:causing a negative inductive current to flow through the secondarywinding; and causing the pair of switches coupled to the secondarywinding to provide a negative output voltage to the switching device,the switching device configured to turn off in response to the negativeoutput voltage.
 19. The method of claim 18, wherein applying the secondvoltage differential across the first and second inputs comprisesapplying a first voltage to the second input; and applying a secondvoltage to the first input, the first voltage higher than the secondvoltage.
 20. The method of claim 19 further comprising: applying thesecond voltage to the second input after a second delay to reduce thenegative current flow through the primary winding while applying thefirst voltage to the second input; and in response to reducing thenegative current flow through the primary winding, cause the pair ofswitches to halt providing the negative output voltage to the switchingdevice.
 21. The method of claim 20 further comprising controlling a dutycycle of the switching device by varying a third delay betweenapplication of the first voltage to the second input after the firstdelay and application of the second voltage to the first input.